On chip interconnects for multiprocessor turbo decoding architectures

Author: A. Baghdadi, Angiolini, Bahl, Benedetto, Benedetto, Benes, Benini, Boutillon, Cooley, Dinoi, Dobkin, Dolinar, Douillard, G. Masera, H. Moussa, Imase, Imase, Kwak, M. Martina, Martina, Masera, Opferman, Papaharalabos, Tarable, Viterbi, Wang, Zhang
Publisher: lsevie

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